The present invention relates to a method of etching hardly-etched materials such as Pt, Ru, Ir, PZT, HfO2 and the like, a semiconductor integrated circuit device including hardly-etched materials, and a method of manufacturing the same, and more particularly, to technologies which are effective in etching a side wall of a hardly-etched material substantially to the perpendicular.
Conventionally, methods of etching semiconductor devices using a tapered photoresist and a rounded-head photoresist are known as means for processing the surface of the semiconductor device.
A method of etching using a tapered mask is disclosed in U.S. Pat. No. 5,818,107 (JP-A-10-214826) and JP-A-10-223855. On the other hand, a method of etching using a rounded photoresist is disclosed in U.S. Pat. No. 6,057,081 (JP-A-10-98162).
However, a non-volatile material, which is difficult to etch (hereinafter simply called a (hardly-etched material), is etched at high temperatures higher than 300xc2x0 C., so that a photoresist may not be available.
With the miniaturization of semiconductor devices and faster operations, investigations are under progress about the use of such materials as alumina, zirconium oxide, hafnium oxide, ruthenium, platinum, tantalum oxide, BST, SBT, PZT and the like for gate insulating films, gate electrodes of MOS (metal-oxide-semiconductor) transistors, and capacitors and capacitor electrodes of memories. In addition, nickel, cobalt, and manganese, or their alloys are used for magnetic-based memories (MRAM: magnetic random access memory) and the like.
Hardly-etched materials may be exemplified by the following materials:
Magnetic Materials: (Applications: Magnetic Disk, MRAM, etc.) Fe, Co, Mn, Ni, etc.
Precious Metals, etc: (Applications: Various Electrodes, etc.)
Pt, Ru, RuO2, Ta, Ir, IrO2, Os, Pd, Au, Ti, TiOx, SrRuO3, (La, Sr)CoO3, Cu, etc.
High Dielectric Materials: (Applications: Capacitors of DRAM (for accumulating charge), etc)
BST: (Ba, Sr)TiO3, SRO: SrTiO3, BTO: BaTiO3, SiTa2O6, Sr2Ta2O7, ZnO, Al2O3, ZrO2, HfO2, Ta2O5, etc.
Ferroelectric Materials: (Applications: Capacitors of FeRAM, etc.)
PZT: Pb(Zr, Ti)O3, PZTN: Pb(Zr,Ti)Nb2O8, PLZT: (Pb, La) (Zr, Ti)O3,
PTN: PbTiNbOx, SBT: SrBi2Ta2O9, SBTN: SrBi2(Ta, Nb)2O9.
BTO: Bi4Ti3O12, BiSiOx, BLOT: Bi4-xLaXTi3O12, etc.
Compound Semiconductors: GaAs, etc.
ITO, etc.: InTiO, etc.
These hardly-etched materials are hard to etch, as compared with such materials as aluminum, silicon, silicon oxide and the like, and therefore present a problem in their difficulties in processing a side wall thereof perpendicularly to a substrate.
Any of the aforementioned known documents does not suggest processing a side wall of a hardly-etched material perpendicularly to a substrate.
Next, the following explanation will be given of reasons for difficulties in etching chemically stable materials to the perpendicular when using a plasma. The chemically stable materials include iron, cobalt, manganese, nickel, platinum, ruthenium, tantalum, alumina, hafnium oxide, zirconium oxide, gallium arsenide and the like.
In the aforementioned hardly-etched materials listed above, which are difficult to etch, a reaction product is produced by etching. The reaction product flies out of the surface of a sample into a vapor phase, and then reaches a wall of an etched material. The reaction product has the nature of readily attaching to the wall of the etched material as it reaches there. If the reaction product attaches only to a position at which the etched material is being etched, this would substantially cause only a reduction in the etching rate. Actually, however, the reaction product attaches to any positions on the etched material. Specifically, the reaction product also attaches to a side wall of the etched material which is not hardly being etched, so that, as a result, the bottom of the etched material is being etched simultaneously with the deposition of the reaction product or a deposition material on the side wall. Consequently, the etching fails to provide the side wall of the etched material perpendicular to the substrate. The foregoing is the cause of the failure in providing a hardly-etched material with its side wall perpendicular to the surface of the substrate in etching the hardly-etched material.
The foregoing reason for the failure in providing an etched material with a side wall perpendicular to a substrate will be explained in greater details with reference to FIGS. 1A through 2G.
FIGS. 1A, 2A illustrate an initial state of etching, where arrows oriented to the right indicate a direction in which a deposition material is deposited, and arrows oriented downward indicate an etching direction. Assume herein that the angle of a side wall of a mask 10 to the top surface of a substrate (taper angle) is at 90 degrees. As a short unit time xcex94t elapses from the initial state, the bottom (the top surface 21 of the etched material 20 exposed to a plasma) is etched by xcex94e, and the deposition material 25 is deposited on the side walls of the mask 10 and the etched material 20 by xcex94d (FIGS. 1B, 2B). Actually, a top surface 30 of the deposition material is also etched, so that the angle xcfx86 of the top surface 30 to the surface of the substrate (taper angle) is determined by the amount xcex94d of the deposition material 25 deposited per unit time (deposition rate), and the amount xcex94e of etching per unit time (etching rate).
In a portion 32 beneath the side wall of the mask 10, at an instance the deposition of the deposition material 25 begins on the side wall of the mask 10, the etching is stopped for a bottom portion 33 of the deposition material on the side wall of the mask 10 (the top surface 21 of the etched material 20 exposed to the plasma). However, at an instance an exposed portion of the etched material 20 is etched in a lower portion of the side wall of the deposition material 25 on the side wall of the mask 10, so that a new side wall of the etched material 20 is exposed, the deposition material is deposited on this exposed surface. Consequently, the etched material 20 is etched in a diagonally downward direction (FIGS. 1C, 2C).
Next, as another unit time xcex94t elapses from the states illustrated in FIGS. 1C, 2C, the deposition material 25 is further deposited on the side wall of the former deposition material 25, while an exposed portion of the etched material 20 is etched in a lower portion of the side wall of the deposition material 25 (FIGS. 1D, 1E, 2D-2F). In this manner, the etching sequentially advances diagonally downward, resulting in an etching shape as illustrated in FIGS. 1F, 2G. Eventually, the side wall of the etched material 20 forms a taper angle xcfx86 (xcfx86 less than 90 degrees) to the surface of the substrate.
It is therefore an object of the present invention to provide a method of etching a hardly-etched material, which is capable of solving the problems inherent in the prior art, as well as a semiconductor fabricating method and apparatus using the etching method.
It is another object of the present invention to provide a method and apparatus for processing the surface of a sample, which is capable of consistently processing a plurality of wafers, or forming a taper angle of an etched material close to the perpendicular, for responding to the requirement for miniaturization of semiconductor devices and the like.
The present invention is characterized by a plasma-based surface processing method which uses a tapered mask to etch a sample or a film formed on a substrate.
Specifically, according to one aspect of the present invention, a plasma-based etching method is provided for etching a film of hardly-etched material formed on a substrate using the film and a mask formed on the hardly-etched film. The method includes the step of etching the film of hardly-etched material using the mask having a side wall angled at less than 90 degrees with respect to the surface of the substrate.
Thus, according to the present invention, for etching a material which is hard to form with a perpendicular side wall, the etched material can be formed with a side wall close to the perpendicular by the use of a tapered mask, thereby fabricating high performance semiconductor devices or highly integrated semiconductor devices.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.